This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to an improved method for making a one-transistor dynamic read/write memory device of the N-channel silicon gate type.
Dynamic read/write memory cells made by the single-level or double-level polysilicon N-channel self-aligned processes commonly used in the industry are shown in my U.S. Pat. No. 4,055,444 as well as in pending U.S. patent applications Ser. No. 648,594, filed Jan. 12, 1976 and Ser. No. 722,841, filed Sept. 13, 1976, by C-K Kuo, all assigned to Texas Instruments; these processes are also shown in Electronics: Feb. 19, 1976, pp. 116-121: May 13, 1976, pp. 81-86; and Sept. 28, 1978, pp. 109-116.
In prior dynamic RAM cell arrays, the "bit" lines (Y or column input/output lines) are usually formed of elongated N+ diffused silicon regions. The capacitance of these bit lines formed of diffused silicon is a continuing problem in large arrays, especially as the capacitor sizes are scaled down for maximum density. One of the most common failure modes in high density dynamic RAMs is that of an inadequate signal level on the bit lines caused by a small storage capacitor to bit line capacitance ratio. This failure mode can be reduced by increasing the supply voltage, by delaying the sensing clock which operates the sense amplifiers, or of course by increasing the area of the storage capacitors or decreasing the capacitor dielectric thickness. These solutions are limited by bar size, access time, cost and yield constraints.
One of the principal contributing factors to the bit line capacitance is the capacitance between the diffused N+ bit line region and the P+ channel stop at the sidewalls. Reduction in this factor by reducing the implant dosage which forms the channel stop will result in an enhanced signal level while still producing an adequately high field threshold voltage. Moreover, the refresh characteristics are improved significantly, especially for the logic 1 state, because the majority of the leakage current is associated with the field implant. Reducing sidewall capacitance has other associated benefits, like improved speed as well as reduced PN junction capacitive loading in the periphery.
It is the principal object of this invention to provide an improved dynamic read/write memory. Another object is to provide a dynamic memory cell array of reduced cell size yet high signal output level. An additional object is to provide a dense array of DRAM memory cells, made by an improved method which provides a reduction in sidewall capacitance for bit lines.